The present invention relates to area CCD imagers.
When CCD imagers are used with more than a minimal on-chip amplifier stage, the constraints of layout typically mean that the charge-sensing node in the amplifier cannot be located exactly at the edge of the array. Thus, a chain of CCD well (dummy pixels) is usually used to transfer the charge packets from the edge of the array to the charge-sensing node in the sense amplifier. However, if a relatively complex sense amplifier is used, such as a correlated double sampling or correlated clamp sample and hold amplifier, timing problems can occur with standard television formats.
That is, in normal CCD area imager architectures, one line of pixels at a time will be transferred in parallel from all the chains of CCD wells into one or more serial registers, and the serial registers will be checked to transfer this line of pixel information successively through a sense amplifier. For level setting, dark reference pixels (shielded from light by, e.g., a metal mask layer) are normally included at the edge of the imaging area. The charge packets from these dark reference locations are clocked through the sense amplifier first, to provide a reference level for subsequent processing stages to reference the image level to. This use of dark reference signals permits compensation for temperature variation, device parameter variations, etc. However, these practices lead to a timing constraint. In the prior art, after one line of charge packets is transferred into the serial register, the serial register must be clocked once for each of the dummy pixels, and then once for each of the dark reference pixels, before any of the charge packets from the imaging area begin to be clocked into the sense amplifier. Since the television format provides a constraint on the total time available per line, this number of CCD clock cycles, at the permissible clock rate for the device parameters used, may be too long. Since the only adjustable parameter in this timing constraint is the number of dummy pixels, this puts an effective limit on the number of dummy pixels which can be interposed between the edge of the array and the sense amplifier charge-sensing node. This in turn implies that it may not be possible to use the more complex amplifier designs, such as correlated double sampling or correlated clamp sample and hold, because their layout would require more dummy pixels between the edge of the array and the charge-sensing node than is permitted by the above time constraint.
This time constraint becomes even worse when more than one serial register is used for output. That is, for a color imager, it is preferable to include a multiplexing stage at the edge of the array, so that each set of three adjacent columns of the CCD array is multiplexed into a sequential output of three charge pockets, which can be transferred in parallel (across the width of the array) into three serial registers. Each serial register can then be clocked through its own sense amplifier, in parallel. However, the use of three sense amplifiers rather than one naturally means that the layout constraints which demand long dummy pixel chains become even worse. Moreover, the time required for the multiplexing gate to operate, and for the parallel transfer of charge packets into three serial registers rather than one, further detracts from the available time. This makes the time constraint even worse.
The present invention solves these problems, and permits use of complex sense amplifiers with multiple serial output registers, by locating the dark reference pixels at the opposite side of the imaging area from that normally used in the prior art. That is, in the prior art the dark reference pixel locations are normally located so that their signals will be clocked through the sense amplifier first, but, in the present invention, the dark reference pixels are located so that they are transferred into the serial register at the location farthest from the sense amplifier, rather than at the end closest to the sense amplifier as in the prior art.
In the present invention, after the charge packets from the imaging area have been clocked along the serial register and through the dummy pixels and into the sense amplifier, the charge packets from the dark reference pixels are not immediately clocked through the sense amplifier, but are left in the dummy pixels during the next parallel transfer of charge packets into the serial register. When the next line of charge packets is clocked through the sense amplifier, the dark reference pixels from the previous line are already stored in the dummy pixels, and waiting to be clocked through the sense amplifier. Thus, the delay component which was due to the number of dummy pixels has been reduced by the number of dark reference pixels which would otherwise be used.
Thus, this area CCD imaging architecture advantageously provides a CCD imager which can operate at standard television timing specifications and still use a complex sense amplifier.
The present invention also advantageously provides a CCD area imager which can operate at standard television timing specifications and also use three separate complex sensing amplifiers.
According to the present invention there is provided: An imager comprising: an image area comprising a plurality of columns of CCD elements, said image area also comprising a dark reference area comprising a further plurality of columns of CCD elements shielded from exposure to light; a storage area, comprising a plurality of columns of CCD elements shielded from exposure to light, and further comprising: a serial shift register, comprising means for receiving packets of charge from respective ones of said columns of CCD elements in said storage area; and an amplifier connected to said serial register at the opposite end from the portion of said serial register which initially receives charge packets generated in said dark reference area from said storage area.